1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to an analog semiconductor integrated circuit and a reference voltage generating circuit having MOS transistors with an effective channel length of about 1 μm or less and fabricated by a submicron CMOS process.
2. Description of the Prior Art
In a MOS transistor, an effective channel length of 1 μm or less makes the electric field around the drain so high as to produce so-called hot carriers, i.e., carriers accelerated to high speed by such an electric field. Hot carriers jump into the gate oxide film of the MOS transistor, varying the threshold level and transconductance of the MOS transistor. Moreover, hot carriers collide with the atoms constituting the semiconductor around the drain and newly produce impact carriers, which generate a substrate current that flows from the drain to the substrate. Hot carriers are especially likely to appear when the drain-to-source voltage of the MOS transistor is high and the gate-to-source voltage is intermediate, i.e., about 1 to 2 V.
This is called the hot carrier problem, which is considered a big problem that lowers the reliability of a semiconductor integrated circuit. To overcome this problem, in a conventional submicron CMOS process, it has been customary to alleviate the electric field around the drain by improving the fabrication process and lowering the supply voltage.
In a case where a MOS transistor is used in a digital semiconductor integrated circuit that uses it as a switching device, when the MOS transistor is completely on, whereas the drain-to-source voltage is low, the gate-to-source voltage is sufficiently high; when the MOS transistor is off, whereas the drain-to-source voltage is high, the gate-to-source voltage is sufficiently low. Thus, hot carriers are likely to appear only during transition periods in which switching takes place. Moreover, even if hot carriers vary the threshold voltage and transconductance of the MOS transistor slightly, this does not greatly affect the operation and function of the digital semiconductor integrated circuit.
Therefore, the aforementioned measures against hot carriers helps to secure satisfactorily high reliability in practical terms. Lowering the supply voltage can increase the transmission delay time through the circuit and thus reduce its operating speed. However, the shorter effective channel length reduces the parasitic capacitance of the MOS transistor and thus enhances the transconductance. This makes the transmission delay time through the MOS transistor eventually shorter than it conventionally is, and therefore, even if the supply voltage is lowered, it is possible to maintain or even enhance the operating speed of the digital semiconductor integrated circuit.
By contrast, in an analog semiconductor integrated circuit that applies an intermediate voltage between the gate and source of a MOS transistor so as to use it as a device for controlling a current, hot carriers are likely to appear especially when the drain-to-source voltage is high. Moreover, this state lasts as long as the MOS transistor operates. Thus, here, as compared with a digital semiconductor integrated circuit in which hot carriers appear only transiently, hot carriers have a more serious effect.
Moreover, analog semiconductor integrated circuits are often required to operate from a wide range of supply voltages, and their circuit configuration does not permit the supply voltage to be lowered sufficiently. Thus, with analog semiconductor integrated circuits, it is not so easy to lower the supply voltage as with digital semiconductor integrated circuits. In addition, variations in the threshold voltage and transconductance of the MOS transistor, which have little effect in digital semiconductor integrated circuits, lead directly to variations in circuit characteristics in analog semiconductor integrated circuits. Furthermore, the substrate current generated by hot carriers makes the drain current and source current of the MOS transistor unequal, causing large errors in circuit characteristics (i.e., large deviations from the current and voltage characteristics as designed).
The serious effect of hot carriers described above has long been preventing analog semiconductor integrated circuits from further miniaturization in applications where a supply voltage of 5 V or higher is required, forcing the use of transistors with effecitge channel lengths of 1 μm or more. On the other hand, analog semiconductor integrated circuits using transistors with effective channel lengths of 1 μm or less operate from a supply voltage as low as 3 V at most so as not to make the drain-to-source voltage too high, and, as described above, their circuit configuration does not permit the supply voltage to be lowered sufficiently. Thus, it has been possible only to fabricate analog semiconductor integrated circuits that operate from a narrow range of supply voltages.
In recent years, however, in response to increasing demand for higher operating speed, lower operating voltage, and lower power consumption in logic semiconductor integrated circuits, facilities based on a CMOS semiconductor fabrication process have been quickly shifting to those designed for effective channel lengths of 1 μm or less, and this has been making increasingly difficult to fabricate analog semiconductor integrated circuits with effective channel lengths of 1 μm or more. Moreover, demand for analog/digital hybrid semiconductor integrated circuits has been increasing the need to mixedly form a logic semiconductor integrated circuit and an analog semiconductor integrated circuit on a single substrate.